Bogong Su

Department of Computer Science
William Paterson University
Office: Science East 5028
Phone: 973-720-2979


Journal Papers

  1. "Software De-Pipelining Technique For Nested Loops", International Journal of Computer Science and Electronics Engineering (IJCSEE) , Vol. 1, No. 1, 2013, with N. Bermudo, A. Krall, and J. Wang
  2. "Performance Analysis of Digital Signal Processors Using SMV Benchmark", International Journal of Signal Processing, Vol. 5, No. 3, Summer 2009, 223-230, with E.W. Hu, C. S. Ku, A. Russo, and J. Wang, 2009
  3. "Building a Retargetable Local Instruction Scheduler", Software Practice and Experience, Vol.28(3), 249-283, March 1998, with V. Allan, S. Beaty, and P. Sweany
  4. "Decomposed Software Pipelining: A New Perspective and A New Approach". International Journal on Parallel Processing, Vol.22, No.3, 1994, with J.Wang and C. Eisenbeis.
  5. "URPR-1: A Single-chip VLIW Architecture", The Euromicro Journal (Microprocessing and Microprogramming), Vol.39, No.1, Dec. 1993, with J. Wang et al.
  6. "Using Timed Petri Net to Model Instruction-Level Loop Scheduling with Resource Constraints", Journal of Computer Science and Technique, Dec. 1993, with C. Eisenbeis and J. Wang.
  7. "Foresighted Compaction under Timing Constraints", IEEE Transactions on Computers, Sept. 1992, with V. Allan et al.
  8. "A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction". IEEE Transactions on Computers, c-32(12):1191-1194, Dec. 1983, with R. Grishman.