Bogong Su

Department of Computer Science
William Paterson University
Office: Science East 5028
Phone: 973-720-2979
E-Mail: sub@wpunj.edu


Peer Reviewed Conference Papers
  1. "Software De-Pipelining Technique For Nested Loops", Proc. of IMCEEME'12, Dec. 2012, with N. Bermudo, A. Krall and J. Wang.

  2. "DSP Performance Comparison by using SMV Benchmark", Proc. of GSPx06, Oct. 2006, with E. Hu, C. S. Ku, A. Russo, and J. Wang.

  3. "New DSP Benchmark based on Selectable Model Vocoder", Proc. of WorldCom'06, June 2006, with E. Hu, C. S. Ku, A. Russo, and J. Wang.

  4. "Analysis of Loop Behavior of Selectable Model Vocoder and Its Impact on Instruction Level Parallelism", Proc. of GSPx2005 Pervasive Signal Processing Conference, Oct. 2005, with E. Hu, J. Wang, and A. Russo.

  5. "Software De-Pipelining Tehnique", Proc. of SCAM 2004, Sept. 2004, with J. Wang, E. Hu, and J. Manzano

  6. "Code Size-Constraint Loop Optimization for DSP Applications", Proc. of EUSIPCO 2004, Sept. 2004, with J. Wang, R. Rabipour, E. Hu, and J. Manzano.

  7. "Assembly Code Conversion of Software Pipelined Loop between two VLIW DSP Processors", Proc. of the International Signal Processing Conference (ISPC03), 2003, with J. Wang, E. Hu, and J. Manzano

  8. "New Source-Level Benchmarking for DSP Processors", Proc. of the International Signal Processing Conference (ISPC03), 2003, with Hu E., Davis k., Hollick M., Manzano J., Regula S., Rellinger S., Wang J., and Leung L.

  9. "De-Pipeline A Software-Pipelined Loop", Proc. of the International Conference on Acoustics, Speech, and Signal Processing(ICASSP2003), 2003, with J. Wang, E. Hu, and J. Manzano

  10. "Assembly Code Conversion Through pattern Mapping Between Two VLIW DSP Processors: A Case Study", Proc. of ICSP'02, Aug. 2002, with J. Wang, E. Hu, and J. Manzano

  11. "A Study of Performance Measurement of DSP Processors", Proc. of MPCS'02 (International Conference on Massively Parallel Computing Systems), April 2002, with E. Hu, K. Davies, M. Hollick, E. Jimenz, E. Rosado, J. Manzano and J. Wang.

  12. “Code Migration from Conventional DSPs to VLIW DSPs”, Proc. of the 11th Annual International Conference on Signal Processing Application & Technology (ICSPAT2000), Oct. 2000, with Jian Wang and Erh-Wen Hu.

  13. “A Scalable Loop Optimization Approach for Scalable DSP Processors”, Proc. of the International Conference on Acoustics, Speech and Signal Processing(ICASSP’2000), June 2000, with Jian Wang and Erh-Wen Hu.

  14. "Impact of Source-Level Loop Optimization on DSP Architecture Design", Proc. of the 10th Annual International Conference on Signal Processing Application & Technology (ICSPAT'99), Nov., 1999, with J. Wang, E. Hu, and A. Esguerra.

  15. “Source-Level Loop Optimization for DSP Code Generation”, Proc. of the International Conference on Acoustics, Speech and Signal Processing (ICASSP’99), March 1999, with J. Wang and A. Esguerra.

  16. “Program Optimization and Compilation for Conventional DSP Processors”, The CASES98 Workshop on Compiler and Architecture Support for Embedded Systems, Dec. 1998, with E. Hu etd.

  17. “Analysis of non-numeric loop programs and its impact on instruction-level loop optimization”, Proc. of the 10th International Conference on Parallel and Distributed Computing and Systems, Oct. 1998, with E. Hu, J. Najarian, H. Grullon, J. Ramirez, A. Ortenzi, J. Wang, and S. Habib.

  18. “Software Pipelining of Nested Loops for Real-time DSP Applications”, Proc. of the International Conference on Acoustics, Speech and Signal Processing(ICASSP’98), May 1998, with J. Wang.

  19. "Ruminate Method -- A Novel Framework for Software Pipelining on Nested Loop". Proc. of the Second International Conference on Massively Parallel Computing Systems, May 1996, Italy, with L. Wang, S. Habib et al.

  20. "SPLIT -- A Hardware/Software Combined Approach for Run-time Pointer Alias Disambiguation", Proc. of Workshop on Academic Electronics in New York State, June 1996, with S. Habib et al.

  21. "A Study of Pointer Aliasing for Software Pipelining using Run-time Disambiguation". Proc. of The 27th Annual ACM/IEEE International Symposium on Microarchitecture(MICRO-27), Nov. 1994, with S. Habib et al.

  22. "GPMB -- Software Pipelining Branch-Intensive Loops", Proc. of The 26th Annual ACM/IEEE International Symposium on Microarchitecture(MICRO-26), Nov. 1993, with Z.Tang et al.

  23. "A VLIW Architecture for Optimal Execution of Branch-Intensive Loops", Proc. of the 25th International Symposium on Microarchitecture(MICRO-25), Dec., 1992, Portland, with W. Zhao and S. Habib.

  24. "GURPR*: A New Global Software Pipelining Algorithm", Proc. of the 24th International Symposium on Microarchitecture(MICRO-24), Albuquerque, Nov. 1991, with J. Wang.

  25. "Overlapped Areas in a Distributed Problem Solving System for Flat-Structured Problems", Proc. of the 4th International Symposium on Artificial Intelligence: Applications in Information, Nov. 1991, Cancun, Mexico, with P. Hu and C. Shi.

  26. "Decomposition and Allocation of Flat-Structured Problems", Proc. of the 15th Annual International Computer Software and Application Conference, Sept. 1991, Tokyo, Japan, with P. Hu and C. Shi.

  27. "Loop-carries Dependence and the General URPR Software Pipelining Approach", Proc. of the 24th HAWAII International Conference on System Science(HICSS-24), Hawaii, Jan. 1991, with J. Wang.

  28. "A Software Pipelining Based VLIW Architecture and Optimizing Compiler", Proc. of the 23rd International Symposium and Workshop on Microprogramming and Microarchitecture(MICRO-23), Orlando, Nov. 1990, with J. Wang et al.

  29. "A Distributed Problem Solving System for Transport Dispatching", Proc. of the 3rd International Conference of IEA/AIE-90, Charleston, July, 1990, with C. Shi et al.

  30. "Global Microcode Compaction with Timing Constraints", Proc. of the 21st Microprogramming Workshop(MICRO-21), San Diego, Nov. 1988, with J. Wang and J. Xia.

  31. "The Architecture of A Distributed Knowledge Base System", Proc. of IFIP WG2.6/WG8.1 Working Conference, Guanzhou, China, June 1988, with C. Shi et al.

  32. "GURPR - A Method for Global Software Pipelining", Proc. of the 20th Microprogramming Workshop(MICRO-20), Colorado Springs, Dec. 1987, with J. Wang and J. Xia.

  33. "Microcode Compaction with Timing Constraints", Proc. of the 20th Microprogramming Workshop(MICRO-20), Colorado Springs, Dec. 1987, with J. Wang and J. Xia.

  34. "URPR - An Extension of URCR for Software Pipelining", Proc. of the 19th Microprogramming Workshop(MICRO-19), New York, Oct. 1986, with S. Ding and J. Xia.

  35. "A case Study in Signal Processing Microprogramming with the URPR Software Pipelining Technique", Proc. of the 19th Microprogramming Workshop(MICRO-19), New York, Oct. 1986, with R. A. Mueller et al.

  36. "Some Experiments in Global Microcode Compaction", Proc. of the 18th Microprogramming Workshop(MICRO-18), Asilomar, CA, Nov. 1985, with S. Ding.

  37. "An Improvement of Trace Scheduling for Global Microcode Compaction", Proc. of the 17th Microprogramming Workshop(MICRO-17), New Orleans, LA, Nov. 1984, with S. Ding and L. Jin.

  38. "Emulating an MIMD Architecture", Proc. of the 15th Microprogramming Workshop(MICRO-15), Palo Alto, CA, 1982, with R. Grishman.