Bogong Su

Department of Computer Science
William Paterson University
Office: Science East 5028
Phone: 973-720-2979
E-Mail: sub@wpunj.edu


Contributed Presentations (Partial list)
  1. "Software De-Pipelining Technique for Nested Loops", presented at the International Conference of Computer, Electrical, Electrical, Electronicsand Mechanical Engineering (IMCEEME'12), Batam, Indonesia, 2012
  2. “Software De-pipelining Technique”, presented at the Fourth IEEE International Workshop on Source Code Analysis and Manipulation (SCAM2004), 2004, Chicago.
  3. “Loop Optimization with Tradeoff between Cycle Count and Code Size for DSP Applications” presented at the XII European Signal Processing Conference (EUSIPCO2004), 2004, Vienna.
  4. "Assembly Code Conversion of Software Pipelined Loop between two VLIW DSP Processors", presented at the International Signal Processing Conference (ISPC03), 2003, Dallas.
  5. "Assembly Code Conversion Through pattern Mapping Between Two VLIW DSP Processors: A Case Study", presented at the ICSP'02, Aug. 2002, Beijing, China.
  6. "A Study of Performance Measurement of DSP Processors", presented at the MPCS'02 (International Conference on Massively Parallel Computing Systems), April 2002, Italy
  7. “Code Migration from Conventional DSPs to VLIW DSPs”, presented at the 11th Annual International Conference on Signal Processing Application & Technology (ICSPAT2000), Oct. 2000, Dallas.
  8. “A Scalable Loop Optimization Approach for Scalable DSP Processors”, presented at the International Conference on Acoustics, Speech and Signal Processing (ICASSP’2000), June 2000, Istanbul, Turkey.
  9. "Impact of Source-Level Loop Optimization on DSP Architecture Design", presented at the 10th Annual International Conference on Signal Processing Application & Technology (ICSPAT'99), Nov., 1999, Orlando.
  10. “Source-Level Loop Optimization for DSP Code Generation”, presented at the International Conference on Acoustics, Speech and Signal Processing (ICASSP’99), March 1999, Phoenix, Arizona, with CS major student Andrew Esguerra.
  11. “Program Optimization and Compilation for Conventional DSP Processors”, presented at the CASES98 Workshop on Compiler and Architecture Support for Embedded Systems, Dec. 1998, Washington DC.
  12. “Analysis of Non-numeric Loop Programs and Its Impact on Instruction-level Loop Optimization”, presented at the 10th International Conference on Parallel and Distributed Computing and Systems, Oct. 1998, Las Vegas.
  13. “Software Pipelining of Nested Loops for Real-Time DSP Applications”, presented at the International Conference on Acoustics, Speech and Signal Processing (ICASSP’98), May 1998, Seattle, WA.
  14. “A Study of Loop Iteration and Other Parameters in Non-numeric Benchmark Programs”, presented at New Jersey Research Consortium Conference, March 1998.
  15. "SPLIT -- A Hardware/Software Combined Approach for Run-time Pointer Alias Disambiguation", presented at the Workshop on Academic Electronics in New York State, June 1996.
  16. "Ruminate Method -- A Novel Framework for Software Pipelining on Nested Loop", presented at the Second International Conference on Massively Parallel Computing Systems, May 1996, Italy.
  17. "A Study of Pointer Aliasing for Software Pipelining using Run-time Disambiguation", presented at the 27th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-27), Nov. 1994.
  18. "GPMB -- Software Pipelining Branch-Intensive Loops", presented at the 26th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-26), Nov. 1993.
  19. "A VLIW Architecture for Optimal Execution of Branch-Intensive Loops", presented at the 25th International Symposium on Microarchitecture (MICRO-25), Dec., 1992, Portland.
  20. "GURPR*: A New Global Software Pipelining Algorithm", presented at the 24th International Symposium on Microarchitecture (MICRO-24), Albuquerque, Nov. 1991.
  21. "A Software Pipelining Based VLIW Architecture and Optimizing Compiler", presented at the 23rd International Symposium and Workshop on Microprogramming and Microarchitecture (MICRO-23), Orlando, Nov. 1990.
  22. "Problem Decomposition in A Distributed Transport Dispatching System", presented at the International Symposium of NGC'89, Beijing, China, April, 1989.
  23. "Global Microcode Compaction with Timing Constraints", presented at the 21st Microprogramming Workshop (MICRO-21), San Diego, Nov. 1988.
  24. "The Architecture of A Distributed Knowledge Base System", presented at IFIP WG2.6/WG8.1 Working Conference, Guanzhou, China, June 1988, with C. Shi et al.
  25. "GURPR - A Method for Global Software Pipelining", presented at the 20th Microprogramming Workshop (MICRO-20), Colorado Springs, Dec. 1987.
  26. "Microcode Compaction with Timing Constraints", presented at the 20th Microprogramming Workshop (MICRO-20), Colorado Springs, Dec. 1987.
  27. "An Improvement of Trace Scheduling for Global Microcode Compaction", presented at the 17th Microprogramming Workshop (MICRO-17), New Orleans, LA, Nov. 1984.